JOB DESCRIPTION
Job Description
•With at least 5 years experience in the related field
•Develop analog architectures and design circuits in FinFET, CMOS or BiCMOS DMOS Processes
•Analyze process nodes, competing architectures and determine the best-in-class implementation for the application.
•Design transistor-level circuits, perform post-layout parasitic-extraction, run pre-layout and back-annotated simulation, analyze parametric design trade-offs, and perform tape-out sign- off using industry leading EDA tools
•Supervise analog layout and able to edit the layout to run experimental simulation.
•Work collaboratively with multiple teams – digital, systems, test, application for silicon bring-up and to ensure DFT, DFM towards better yield during production.
•Perform post-layout parasitic-extraction and back-annotated simulations to validate design
•Initiate R&D for root cause failures, investigate anomalous observations in silicon across PVT corners, and be able to conclude a solution.
JOB QUALIFICATION
Requirements
- Proven track record in one of the following areas:
- Power Management: POR, Voltage & Current references, Buck/Boost converters based on PWM/PFM/COT architectures
- Serial Links: USB/MIPI/HDMI/LVDS/DDR/LPDDR/SERDES
- Data Converters: SAR/Pipeline/Hybrid with enob 8-14 bits
- Proficiency with EDA tools including Cadence Virtuoso, Spectre, ADE, Mixed-mode AMS tools, Layout XL.
- Extensive knowledge of layout effects for circuit and layout design. Ability to supervise layout engineers.
- Extensive experience with post-layout extraction, simulation across PVT and physical verification through tape-out sign-off.
- Experience with silicon bring-up, characterization, qualification, and meet production release criteria
- Ability to communicate and work effectively with geographically dispersed teams of mixed-signal and digital engineers
- Ability to work independently, analyze complex problems and drive solutions.
- Have an entrepreneurial passion to drive technology and business.
OTHER JOB REQUIREMENTS
WORK LOCATION
PasigCOMPANY PREVIEW
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COMPANY OVERVIEW
Marquee Semiconductor is a “Spec to FPGA/ACAP/Silicon Solution” provider. The company is founded and advised by Semiconductor industry veterans, who are based in Silicon Valley USA for 25+ years, with leadership experience at many leading companies. The company focuses on 3 verticals: AI/ML implementation leveraging FPGAs and ACAP devices, Silicon/FPGA/ACAP based Digital Solution and Analog/Mixed Signal Solution. The company’s engineering strengths are in CNN/RNN, Algorithms/C++/HLS, SystemVeri
The company prides itself to work with customers as partners in a wholesome approach towards providing solutions that goes beyond the immediate product line into the future roadmap. With engineering around the world – Philippines, India, Singapore and the USA, Marquee differentiates itself with its DRIVE model – Domain expertise, R&D enablement, IP Infrastructure, Velocity of Execution, and Ecosystem Partnership.